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RISC-V Instruction Set Extensions for Lightweight Symmetric Cryptography
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| Abstract: | The NIST LightWeight Cryptography (LWC) selection process aims to standardise cryptographic functionality which is suitable for resource-constrained devices. Since the outcome is likely to have significant, long-lived impact, careful evaluation of each submission with respect to metrics explicitly outlined in the call is imperative. Beyond the robustness of submissions against cryptanalytic attack, metrics related to their implementation (e.g., execution latency and memory footprint) form an important example. Aiming to provide evidence allowing richer evaluation with respect to such metrics, this paper presents the design, implementation, and evaluation of one separate Instruction Set Extension (ISE) for each of the 10 LWC final round submissions, namely Ascon, Elephant, GIFT-COFB, Grain-128AEADv2, ISAP, PHOTON-Beetle, Romulus, Sparkle, TinyJAMBU, and Xoodyak; although we base the work on use of RISC-V, we argue that it provides more general insight. |
BibTeX
@article{tches-2022-32685,
title={RISC-V Instruction Set Extensions for Lightweight Symmetric Cryptography},
journal={IACR Transactions on Cryptographic Hardware and Embedded Systems},
publisher={Ruhr-Universität Bochum},
volume={2023, Issue 1},
pages={193-237},
url={https://tches.iacr.org/index.php/TCHES/article/view/9951},
doi={10.46586/tches.v2023.i1.193-237},
author={Hao Cheng and Johann Großschädl and Ben Marshall and Dan Page and Thinh Pham},
year=2022
}